View LP62S1024BX-55LLI_8541853.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

lp62s1024b - i series preliminary 128k x 8 bit low voltage cmos sram preliminary (october, 2002, version 0.1) amic technology, corp. document title 128k x 8 bit low voltage cmos sram revision history rev. no. history issue date remark 0.0 initial issue may 30, 2002 preliminary 0.1 add 32l p b - free tssop package type october 2, 2002
lp62s1024b - i series preliminary 128k x 8 bit low voltage cmos sram preliminary (octob er, 2002, version 0.1) 1 amic technology, corp. features general description n power supply rang e: 2.7v to 3.6v n access times: 55/70 ns (max.) n current: very low power version: operating: 30ma(max.) standby: 5ua (max.) n full static operation, no clock or refreshing required n all inputs and outputs are directly ttl - compatible n common i/o us ing three - state output n output enable and two chip enable inputs for easy application n data retention voltage: 2v (min.) n available in 32 - pin sop, tsop, tssop (8 x 13.4mm) forward type and 36 - pin csp packages the lp62s1024b - i is a low operating current 1,048,576 - bit static random access memory organized as 131,072 words by 8 bits and operates on a low power voltage: 2.7v to 3.6v. it is built using amic's high performance cmos process. inputs and three - state outputs are ttl compatible and allow for direc t interfacing with common system bus structures. two chip enable inputs are provided for power - down and device enable and an output enable input is included for easy interfacing. data retention is guaranteed at a power supply voltage as low as 2v. product family power dissipation product family operating temperature vcc range speed data retention (i ccdr , typ.) standby (i sb1 , typ.) operating (i cc2 , typ.) package type lp62s1024b - 40 c ~ +85 c 2.7v~3.6v 55ns / 70ns 0.05 m a 0.08 m a 1.5ma 32l sop 32l tso p 32l tssop 36b m bga 1. typical values are measured at vcc = 3.0v, t a = 25 c and not 100% tested. 2. data retention current vcc = 2.0v.
lp62s1024b - i series preliminary (october, 2002, version 0.1) 2 amic technology, corp. pin configurations n n sop n n tsop/tssop n n csp (chip size package) 36 - pin top view nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o 1 i/o 2 i/o 3 i/o 4 gnd i/o 5 i/o 6 i/o 7 i/o 8 a10 a9 a8 a13 ce2 a15 vcc a11 lp62s1024bm-i 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 oe lp62s1024bv-i (lp62s1024bx-i) 1 16 17 32 ce1 we a0 i/o 5 i/o 6 gnd vcc i/o 7 i/o 8 a9 a10 oe a11 ce1 a12 a13 a14 a16 nc nc a15 i/o 4 i/o 3 i/o 2 i/o 1 gnd vcc a1 a2 ce2 we nc a5 a4 a3 a6 a7 a8 6 5 4 3 2 1 a b c d e f g h pin no. pin name pin no. pin name 1 2 a9 3 4 5 6 7 8 9 10 11 12 13 14 30 29 28 27 26 25 24 22 19 21 20 23 18 17 a8 a13 ce2 a15 vcc nc i/o 8 a16 a14 a12 a7 a6 a3 a2 a1 a0 i/o 1 i/o 2 gnd i/o 4 i/o 5 i/o 6 i/o 7 i/o 3 a11 we ce1 15 16 31 32 a5 a4 a10 oe block diagram row decoder 512 x 2048 memory array input data circuit column i/o control circuit ce2 ce1 we i/o 8 i/o 1 a16 a15 a14 a0 vcc gnd oe
lp62s1024b - i series preliminary (october, 2002, version 0.1) 3 amic technology, corp. pin descriptions - sop pin no. symbol description 1 nc no connection 2 - 12, 23, 25 - 28, 31 a0 - a16 address inputs 13 - 15, 17 - 21 i/o 1 - i/o 8 data input/outputs 16 gnd ground 22 ce1 chip enable 24 oe output enable 29 we write enable 30 ce2 chip enable 32 vcc power supply pin description ? tsop/tssop pin no. symbol description 1 - 4, 7, 10 - 20, 31 a0 - a16 address inputs 5 we write enable 6 ce2 chip enable 8 vcc power supply 9 nc no connection 21 - 23, 25 - 29 i/o 1 - i/o 8 data input/outputs 24 gnd ground 30 ce1 chip enable 32 oe output enable pin description - csp symbol description symbol description a0 - a16 address inputs nc no connection we write enable i/o 1 - i/o 8 data input/output oe output enable vcc power supply ce1 chip enable gnd ground ce 2 chip enable -- --
lp62s1024b - i series preliminary (october, 2002, version 0.1) 4 amic technology, corp. recommended dc operating conditions (t a = - 40 c to +85 c) symbol parameter min. typ. max. unit vcc supply voltage 2.7 3.0 3.6 v gnd ground 0 0 0 v v ih input high voltage 2.2 - vcc + 0.3 v v il input low voltage - 0.3 - +0.6 v c l output load - - 30 pf ttl output load - - 1 - absolute maximum ratings* vcc to gnd ................................ .............. - 0.5v to +4.6v in, in/out volt to gnd ..................... - 0.5v to vcc +0.5v operating temperature, topr ................... - 40 c to +85 c storage temperature, tstg ..................... - 55 c to +125 c temperature under bias, tb ias ................ - 10 c to +85 c power dissipation, p t ................................ ............... 0.7w *comments stresses above those listed under "absolute maximum ratings" may cause permanent damage to this device. these are stress ratings only. functional operation of this device at these or any other con ditions above those indicated in the operational sections of this specification is not implied or intended. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. dc electrical characteristics (t a = - 40 c to +85 c, vcc = 2.7v to 3.6v, gnd = 0v) symbol parameter lp62s1024b - 55lli/70lli unit conditions min. max. ? i li input leakage current - 1 m a v in = gnd to vcc ? i lo output leakage current - 1 m a ce1 = v ih or ce2 = v il or oe = v ih or we = v il v i/o = gnd to vcc i cc active power supply current - 3 ma ce1 = v il , ce2 = v ih i i/o = 0ma i cc1 dynamic operating - 30 ma min. cycle, duty = 100% ce1 = v il , ce2 = v ih i i/o = 0ma i cc2 current - 3 ma ce1 = v il , ce2 = v ih v ih = vcc, v il = 0v f = 1 mh z, i i/o = 0ma
lp62s1024b - i series preliminary (october, 2002, version 0.1) 5 amic technology, corp. dc electr ical characteristics (continued) symbol parameter lp62s1024b - 55lli/70lli unit conditions min. max. i sb - 0.5 ma vcc 3.3v ce1 = v ih or ce2 =v il i sb1 standby power supply current - 5 m a vcc 3.3v ce1 3 vcc - 0.2v or ce2 0.2v v in 3 0v v ol output low voltage - 0.4 v i ol = 2.1ma v oh output high voltage 2.2 - v i oh = - 1.0ma truth table mode ce1 ce2 oe we i/o operation supply current standby h x x x high z i sb , i sb1 x l x x high z i sb , i sb2 output disable l h h h high z i cc, i cc1, i cc2 read l h l h d out i cc, i cc1, i cc2 write l h x l d in i cc, i cc1, i cc2 note: x = h or l capacitance (t a = 25 c, f = 1.0mhz) symbol parameter min. max. unit conditions c in * input capacitance 6 pf v in = 0v c i/o * input/output capacitance 8 pf v i/o = 0v * these parameters are sampled and not 100% tested.
lp62s1024b - i series preliminary (october, 2002, version 0.1) 6 amic technology, corp. ac characteristics (t a = - 40 c to +85 c, vcc = 2.7v to 3.6v) symbol parameter lp62s1024b - 55lli lp62s1024b - 70lli unit min. max. min. max. read cycle t rc read cycle time 55 - 70 - ns t aa address access time - 55 - 70 ns t ace1 chip enable access time ce1 - 55 - 70 ns t ace2 ce2 - 55 - 70 ns t oe output enable to output valid - 30 - 35 ns t clz1 chip enable to output in low z ce1 10 - 10 - ns t clz2 ce2 10 - 10 - ns t olz output enable to output in low z 5 - 5 - ns t chz1 chip disable to output in high z ce1 0 20 0 25 ns t chz2 ce2 0 20 0 25 ns t ohz output disable to output in high z 0 20 0 25 ns t oh output hold from address change 5 - 10 - ns write cycle t wc write cycle time 55 - 70 - ns t cw chip enable to end of write 50 - 60 - ns t as ad dress setup time 0 - 0 - ns t aw address valid to end of write 50 - 60 - ns t wp write pulse width 40 - 50 - ns t wr write recovery time 0 - 0 - ns t whz write to output in high z 0 25 0 25 ns t dw data to write time overlap 25 - 30 - ns t dh data hold fro m write time 0 - 0 - ns t ow output active from end of write 5 - 5 - ns notes: t chz1 , t chz2 , t ohz , and t whz are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels.
lp62s1024b - i series preliminary (october, 2002, version 0.1) 7 amic technology, corp. timing waveforms read cycle 1 (1, 2, 4) t rc t oh t aa t oh address d out read cycle 2 (1, 3, 4, 6) t clz1 5 t ace1 t chz1 5 ce1 d out read cycle 3 (1, 4, 7, 8) t clz2 5 t ace2 t chz2 5 ce2 d out
lp62s1024b - i series preliminary (october, 2002, version 0.1) 8 amic technology, corp. timing waveforms (continued) read cycle 4 (1) t rc address ce2 d out t aa t oe t olz 5 t ace1 t clz1 5 t ace2 t clz2 5 t chz2 5 t ohz 5 t chz1 5 t oh oe ce1 notes: 1 . we is high for read cycle. 2. device is continuously enabled ce1 = v il and ce2 = v ih . 3. address valid prior to or coincident with ce1 transition low. 4. oe = v il . 5. transition is measured 500mv from steady state. this parameter is sampled and not 100% tested. 6. ce2 is high. 7. ce1 is low. 8. address valid prior to or coincident with ce2 transition high.
lp62s1024b - i series preliminary (october, 2002, version 0.1) 9 amic technology, corp. timing waveforms (continued) wri te cycle 1 (6) (write enable controlled) t wc address ce1 ce2 d in t ow t dh t dw t whz t wp 2 t as 1 (4) t cw 5 t aw t wr 3 we d out (4)
lp62s1024b - i series preliminary (october, 2002, version 0.1) 10 amic technology, corp. timing waveforms (continued) write cycle 2 (chip enable controlled) t wc address ce1 ce2 d in t dh t dw (4) (4) t cw 5 t aw t wr 3 we d out t whz 7 t wp 2 t cw 5 t as 1 notes: 1. t as is measured from the address valid to the beginning of write. 2. a write occurs during the overlap (t wp ) of a low ce1 , a high ce2 and a low we . 3. t wr is measured from the earliest of ce1 or we going high or ce2 going low to the end of the write cycle. 4. if the ce1 low transition or the ce2 high transition occurs simultaneously with the we low transition or after the we transition, outputs remain in a high impedance state. 5. t cw is measured from the later of ce1 going low or ce2 going high to the end of write. 6. oe is continuously low. ( oe = v il ) 7. transition is measured 500mv from steady state. this para meter is sampled and not 100% tested.
lp62s1024b - i series preliminary (october, 2002, version 0.1) 11 amic technology, corp. ac test conditions input pulse levels 0.4v to 2.4v input rise and fall time 5 ns input and output timing reference levels 1.5v output load see figures 1 and 2 30pf * including scope and jig. * including scope and jig. c l ttl 5pf c l ttl figure 1. output load figure 2. output load for t clz1 , t clz2 , t ohz , t olz , t chz1 , t chz2 , t whz , and t ow data retention characteristics (t a = - 40 c to 85 c) symbol parameter min. max. unit conditions v dr1 2.0 3.6 v ce1 3 vcc - 0.2v v dr2 vcc for data retention 2.0 3.6 v ce2 0.2v, i ccdr1 data retention current - 3* m a vcc = 2v, ce1 3 vcc - 0.2v, v in 3 0v i ccdr2 - 3* m a vcc = 2v, ce2 0.2v, v in 3 0v t cdr chip disable to data retention time 0 - ns see retention waveform t r operation recovery time 5 - ms * lp62s1024b - 55lli/70lli i ccdr : max. 3 m a at t a = 0 c to + 40 c
lp62s1024b - i series preliminary (october, 2002, version 0.1) 12 amic technology, corp. low vcc data retention waveform (1) ( ce1 controlled) vcc ce1 t cdr v ih 3.0v t r v ih 3.0v data retention mode v dr 3 2v ce1 3 v dr - 0.2v low vcc data retent ion waveform (2) (ce2 controlled) vcc ce2 t cdr v il 3.0v t r v il 3.0v data retention mode v dr 3 2v ce2 0.2v
lp62s1024b - i series preliminary (october, 2002, version 0.1) 13 amic technology, corp. ordering information part no. access time (ns) operating current max. (ma) standby current max. ( m m a) package lp62s1024bm - 55lli 32l sop lp62s1024bv - 55lli 32l tsop lp62s1024bx - 55 lli 32l tssop lp62s1024bx - 55llif 32l pb - free tssop lp62s1024bu - 55lli 55 30 5 36l csp lp62s1024bm - 70lli 32l sop lp62s1024bv - 70lli 32l tsop lp62s1024bx - 70lli 32l tssop lp62s1024bx - 70llif 32l pb - free tssop lp62s1024bu - 70lli 70 30 5 36l csp
lp62s1024b - i series preliminary (october, 2002, version 0.1) 14 amic technology, corp. package information sop (w.b.) 32l outline dimensions unit: inches/mm 1 e h e l l e c 16 see detail f detail f 17 32 e 1 e 1 a 1 a 2 a s d seating plane d y e b ~ ~ symbol dimensions in inches dimensions in mm a 0.118 max. 3.00 max. a 1 0.004 min. 0.10 min. a 2 0.1060.005 2.690.13 b 0.016 +0.004 0.41 +0.10 - 0.00 2 - 0.05 c 0.008 +0.004 0.20 +0.10 - 0.002 - 0.05 d 0.805 typ. (0.820 max.) 20.45 typ. (20.83 max.) e 0.4450.010 11.300.25 e 0.050 0.006 1.270.15 e 1 0.525 nom. 13.34 nom. h e 0.5560.010 14.120.25 l 0.0310.008 0.790.20 l e 0.0550.00 8 1.400.20 s 0.044 max. 1.12 max. y 0.004 max. 0.10 max. q 0 ~ 10 0 ~ 10 notes: 1. the maximum value of dimension d includes end flash. 2. dimension e does not include resin fins. 3. dimension e 1 is for pc board surface mount pad pitch design ref erence only. 4. dimension s includes end flash.
lp62s1024b - i series preliminary (october, 2002, version 0.1) 15 amic technology, corp. package information tsop 32l type i (8 x 20mm) outline dimensions unit: inches/mm e l e l gauge plane a a 2 c 0.25 bsc detail "a" d y detail "a" s a 1 b h d d e 0.10(0.004) m 12.0 q symbol dimensions in inches dimensions in mm a 0.047 max. 1.20 max. a 1 0.0040.002 0.100.05 a 2 0.0390.002 1.000.05 b 0.0080.001 0.200.03 c 0.0060.001 0.150.02 d 0.7240.004 18.400.10 e 0.3150.004 8.000.10 e 0.020 typ. 0.50 typ. h d 0.7870.007 20.000.20 l 0.0200.004 0.500.10 l e 0.031 typ. 0.80 typ. s 0.0167 typ. 0.425 typ. y 0.004 max. 0.10 max. q 0 ~ 6 0 ~ 6 notes: 1. the maximum value of dimension d includes end flash. 2. dimension e does not include resin fins. 3. dimension e 1 is for pc board surface mount pad pitch design reference only. 4. dimension s includes e nd flash.
lp62s1024b - i series preliminary (october, 2002, version 0.1) 16 amic technology, corp. package information tssop 32l type i (8 x 13.4mm) outline dimensions unit: inches/mm e detail "a" d 0.10mm detail "a" s b d 1 e d l e l gauge plane a a 2 c 0.25 bsc detail "a" a 1 seating plane 12.0 q symbol dimensions in inches dimensions in mm a 0.049 max. 1.25 max. a 1 0.002 min. 0.05 min. a 2 0.0390.002 1.000.05 b 0.008 0.001 0.200.03 c 0.0060.0003 0.150.008 e 0.3150.004 8.000.10 e 0.020 typ. 0.50 typ. d 0.5280.008 13.400.20 d 1 0.4650.004 11.800.10 l 0.020.008 0.500.20 l e 0.0266 min. 0.675 min. s 0.0109 typ. 0.278 typ. y 0.004 max. 0.10 max. q 0 ~ 6 0 ~ 6 notes: 1. the maximum value of dimension d includes end flash. 2. dimension e does not include resin fins. 3. dimension e 1 is for pc board surface mount pad pitch design reference only. 4. dimension s includes end flash.
lp62s1024b - i series preliminary (october, 2002, version 0.1) 17 amic technology, corp. package information 36ld csp (6 x 8 mm) outline dimensions unit: mm a 1 a 2 a b c d e f g h top view ball#a1 corner side view c seating plane // 0.25 c a (0.36) a b c d e f g h 1 2 3 4 5 6 1 2 3 4 5 6 c 0.10 c s 0.25 s a b b (36x) bottom view ball*a1 corner e e 1 e b e d 1 d a 0.20(4x) 0.10 c dimensions in mm symbol min. nom. max. a 1.00 1.10 1.20 a 1 0.16 0.21 0.26 a 2 0.48 0.53 0.58 d 5.80 6.00 6.20 e 7.80 8.00 8.20 d 1 --- 3.75 --- e 1 --- 5.25 --- e --- 0 .75 --- b 0.25 0.30 0.35 note: 1. the ball diameter, ball pitch, stand - off & package thickness are different from jedec spec mo192 (low profile bga family). 2. primary datum c and seating plane are defined by the spherical crowns of the solder balls. 3. dime nsion b is measured at the maximum. 4. theere shall be a minimum clearance of 0.25mm between the edge of the solder ball and the body edge.

▲Up To Search▲

Price & Availability of LP62S1024BX-55LLI

	To Download LP62S1024BX-55LLI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .